IEEE_VLSI_PROJECT TITLES_2014
CMOS
1.
Quaternary
Logic Lookup Table in Standard CMOS.
2.
Universal
Set of CMOS Gates for the Synthesis of Multiple Valued Logic Digital Circuits.
3.
Scalable
Digital CMOS Comparator Using a Parallel Prefix Tree.
4.
A
High Performance modulo 2n+1 Squarer Design Based on Carbon Nanotube
Technology.
5.
Low-power
compact composite field AES S-Box/Inv S-Box design in 65 nm CMOS using Novel
XOR Gate.
6.
A
proposed eleven-transistor (11-T) CMOS SRAM cell for improved read stability
and reduced read power consumption.
7.
Performance
Analysis of Novel Domino XNOR Gate in Sub 45nm CMOS Technology.
MULTIPLIERS
8.
Low
Power 64bit Multiplier Design by Vedic Mathematics.
9.
Design
and Implementation of 32-Bit Vedic Multiplier On FPGA.
10. Design and FPGA Implementation of
High Speed Vedic Multiplier.
11. Implementation of High Speed
Multiplier on FPGA.
12. Design of High Speed, Area Efficient,
Low Power Vedic Multiplier using Reversible Logic Gate.
13. An Efficient High Speed Wallace Tree
Multiplier.
14. Design and Implementation of
High-Speed and Energy-Efficient Variable-Latency Speculating Booth Multiplier
(VLSBM).
AES
15. FPGA-Based 40.9-Gbits/s Masked AES
with Area Optimization for Storage Area Network.
16. A Hybrid Fault Tolerant Approach for
AES.
17. Efficient AES-GCM for VPNs Using
FPGAs.
18. An Efficient VLSI Implementation of
Low Power AES – CTR.
19. Hardware efficiency comparison of AES
Implementations.
20. A
Secure Software Implementation of
Nonlinear AES S-Box with
the Enhancement of
Biometrics.
DIGITAL
21. Split-path Fused Floating Point
Multiply Accumulate (FPMAC).
22. Area–Delay–Power Efficient
Carry-Select Adder.
23. Recursive Approach to the Design of a
Parallel Self-Timed Adder.
24. The Floating-Point Unit of the Jaguar
x 86 Cores.
FILTERS
25. Bit-Level Optimization of Adder-Trees
for Multiple Constant Multiplications for Efficient FIR Filter Implementation.
26. Area-Delay-Power Efficient
Fixed-Point LMS Adaptive Filter With Low Adaptation-Delay.
27. Design and Evaluation of
High-Performance Processing Elements for Reconfigurable Systems.
28. Low-Power Logarithmic Number System
Addition/Subtraction and their Impact on Digital Filters.
29. FPGA based Architectures for High
Performance Adaptive FIR Filter Systems.
30. Design of Digit-Serial FIR Filters:
Algorithms, Architectures, and a CAD Tool.
31. Low-Cost FIR Filter Designs Based on
Faithfully Rounded Truncated Multiple Constant Multiplication/Accumulation.
32. Low Power FPGA Implementation of
Digital FIR Filter Based on Low Power Multiplexer Base Shift/Add Multiplier.
33. Area-Efficient Parallel FIR Digital
Filter Structures for Symmetric Convolutions Based on Fast FIR Algorithm.
NETWORK ON CHIP
34. Achieving High-Performance On-Chip
Networks with Shared-Buffer Routers.
35. Variable-Pipeline-Stage Router.
36. Path-Congestion-Aware Adaptive
Routing with a Contention Prediction Scheme for Network-on-Chip Systems.
37. Hybrid Path-Diversity-Aware Adaptive
Routing with Latency Prediction Model in Network-on-Chip Systems.
38. Smart-reliable-network on chip.
COMMUNICATION
39. MIMO-OFDM Transceivers with
Dual-Polarized Division Multiplexing and Diversity for Multimedia Broadcasting
Services.
40. Low-Power Correlation for IEEE 802.16
OFDM Synchronization on FPGA.
41. A Weighted OFDM Signal Scheme for
Peak-to-Average Power Ratio Reduction of
OFDM Signals.
42. Pipelined Radix-
Feed forward FFT Architectures.
43. Area and Delay Minimization of
Radix-2k Feed forward FFT Architecture.
44. High Throughput Radix-2k Feedforward
FFT Architectures.
REVERSIBLE
45. A New CRL Gate as Super Class of
Fredkin Gate to DesignReversible Quantum Circuits.
46. Testing Reversible Adder/Subtractor
for Missing Control Points.
47. Design of 4 -Bit Reversible Shift
Registers.
48. A Novel Design Approach to Achieve
Fault Coverage in Sequential Circuits.
49. Design and Implementation of Testable
Reversible Sequential Circuits Optimized Power.
50. Design and Analysis of Parity
Preserving Fault Tolerant Reversible Logic Shift Registers Using New 4*4
RR-Gates.
51. Design of High Speed Low Power
Reversible Logic Adder Using HNG Gate.
52. Implementation of an 8 -bit Low-power
Multiplier based on Reversible Gate Technology.
53. Design of High Speed, Area Efficient,
Low Power Vedic Multiplier using Reversible Logic Gate.
IMAGE PROCESSING
54. Multiplier Based and Canonical Signed
Digit Based VLSI Architecture for Discrete Wavelet Transformation.
55. A Pipeline VLSI Architecture for Fast
Computation of the 2-D Discrete Wavelet Transform.
56. An Efficient VLSI Architecture for
Lifting-Based Discrete Wavelet Transform.
57. Memory-Efficient High-Speed
Convolution-based Generic Structure for Multilevel 2-D DWT.
ANTENNA
- The U-Shaped Structure in Dual-Band Circularly
Polarized Slot Antenna Design
- Circularly Polarized Chip Antenna Design for
GPS Reception on Handsets
- Design of Orthogonal MIMO Handset Antennas
Based on Characteristic Mode Manipulation at Frequency Bands Below 1 GHz
- A Compact Dual-Band Pattern Diversity Antenna
by Dual-Band Reconfigurable Frequency-Selective Reflectors With a Minimum
Number of Switches
- Differentially Fed Dual-Band Implantable
Antenna for Biomedical Applications
- A Dual Band Micro strip-Fed Slot Antenna
- Development of a Linearly Polarized
Cavity-Backed Antenna Using HMSIW Technique
- Development of a Low-Profile Circularly
Polarized Cavity-Backed Antenna Using HMSIW Technique
- An Improved PSO Algorithm and Its Application
to UWB Antenna Design
- Wideband Circularly Polarized Dielectric
Bird-Nest Antenna With Conical Radiation Pattern
- An Integrated Diversity Antenna Based on
Dual-Feed Cavity-Backed Slot
- Performance Improvement of Microstrip Patch
Antenna using Left-Handed Metamaterial
- A Novel Approach for Analysis of Bandwidth of
Micro strip Patch Antenna Using Neural Network
- Review Paper on Phased Array Microstrip Patch
Antenna
- Circular Shape Antenna Embedded with b-Shape
Slot for UWB Applications
- Design of A Novel Reconfigurable Fractal
Antenna for Multi-Band Application
- design and analysis of minkowski fractal
antenna using microstrip feed
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